Deep trench configurations are commonly used in semiconductor devices, for example, as storage capacitor components for memory cell devices. In such a case, each discrete memory cell device may include a deep trench configuration coupled to a planar device, such as a switching or gate transistor which controls the charge held by the deep trench configuration. In order to form an electrical connection between a portion of the planar device formed at the planar semiconductor substrate surface and an interior of the deep trench configuration, material that can be made conductive is formed between the deep trench configuration and the planar device. This material is commonly referred to as a strap.
The memory cell device described above represents information based upon whether or not the deep trench configuration is charged. In general, shallow trench isolation (STI) may be used to isolate discrete memory cell devices to prevent interference therebetween. Accordingly, shallow isolation trenches are formed between adjacent deep trench configurations to ensure that they operate independently. However, shallow trench isolation of two closely located deep trench configurations, as well as individual strap formation for each of the deep trench configurations, requires meticulous adjustment of pertinent fabrication processes such as lithography and etching, especially when the closest distance between trenches falls below 0.25 .mu.m. As a result, the fabrication process tolerance is narrowed and stringent quality control of each processing step is required. Therefore, the memory cell devices are difficult to manufacture. Some of these problems associated with device manufacture will be illustrated by the following example.
FIG. 1 illustrates a portion of a composite body 100 including a semiconductor substrate 110 having a pad oxide layer 120, for example, SiO.sub.2, formed thereon. The semiconductor substrate 110 may be formed of, for example, crystal silicon. A layer 130 is formed over the pad oxide layer 120. The layer 130 may be formed of a nitride, such as Si.sub.3 N.sub.4. Of course, other silicon nitride compounds, e.g. Si.sub.3.+-.x N.sub.4.+-.y, may be used depending on the characteristics desired. The oxide layer 120 and the nitride layer 130 serve as masks for pertinent fabrication processes such as etching, oxidation, and/or chemical-mechanical polishing (CMP), for example. First and second deep trenches 140, 150 are formed in the nitride layer 130, the oxide layer 120, and the semiconductor substrate 110. A nitride region 135, an oxide region 125, and a semiconductor substrate region 115 are disposed between deep trenches 140, 150. First and second deep trench configurations 142, 152 are constructed in first and second deep trenches 140, 150, respectively.
Each of first and second trench configurations 142, 152 includes a thin insulator film 144, 154 formed on the interior surface of the trench 140, 150, a thick insulator film 146, 156 formed over the thin insulator film 144, 154 at a middle portion of the trench 140, 150, and storage node material 147, 157 formed to fill the inside of the respective deep trenches 140, 150 to the height of the thin insulator film 144, 154 and the thick insulator film 146, 156. However, filling the deep trenches 140, 150 is difficult because of their high aspect ratios. As a result, voids 148, 158 are formed in the storage node material 147, 157. Strap material 149, 159 is formed on top of the thin insulator film 144, 154, the thick insulator film 146, 156, and the storage node material 147, 157 to fill the interior of the deep trenches 140, 150 to a level somewhere below the surface of the semiconductor substrate 110. Therefore, the strap material 149, 159 directly contacts with both the semiconductor substrate 110 around the deep trench configurations 142, 152 and the top of the storage node material 147, 157 as illustrated in FIG. 1.
The thin insulator films 144, 154 may be formed of silicon nitride, for example, Si.sub.3 N.sub.4, and serve to form a capacitance between the storage node material 147, 157 and the semiconductor substrate 110. The thick insulator films 146, 156, which may be formed by chemical vapor deposition (CVD) of tetraethylorthosilicate (TEOS) Si(OC.sub.2 C.sub.5).sub.4, isolates the storage node material 147, 157 from the surrounding semiconductor substrate 110. Storage node material 147, 157 serve as storage nodes, and may be formed of, for example, n+ polysilicon. The strap material 149, 159 may be formed from intrinsic polycrystalline silicon.
When the composite body 100 is constructed as a part of memory device, STI is used to electrically isolate deep trench configurations 142, 152 from one another and to delineate the regions on which planar devices are formed. It should be noted that before STI formation processes are initiated, all storage nodes are connected to the semiconductor substrate 110 by the straps 149, 159. After shallow trench formation, insulating material is used to fill the shallow trenches up to the surface of the composite body 100. Thus, after completion of STI formation processes, straps as well as deep trenches are completely buried beneath the insulating film. This type of strap formation, i.e. buried strap, is advantageous because it allows subsequent processes to be completed on a planar surface. Flat topography is critical to produce excellent resolution in lithography. Planar devices, including switching transistors coupled to the respective deep trench configurations 142, 152, are then fabricated using surface device fabrication techniques currently known in the art.
Conventionally, portions of the first and second deep trench configurations 142, 152 are etched together with nitride region 135, oxide region 125, and semiconductor substrate 115 in a region indicated by 160 in FIG. 1. This ensures isolation between adjacent deep trench configurations despite slight misalignment and poor resolution in the lithographic stage of the STI process. In addition, capacitive coupling between the storage node of a deep trench configuration and gate material running above it can be reduced. To effect the etch, a resist layer is formed over the composite body 100 illustrated in FIG. 1 and developed to form a pattern for etching. FIG. 2 illustrates a shallow trench 210 formed between the first and second deep trench configurations 142, 152 by etching the composite body 100 through opening 220 in resist layer 230 according to conventional techniques. However, several disadvantages and difficulties exist when the shallow trench is formed by such conventional technique.
First, as can be seen most clearly in FIG. 1, the upper surface of the composite body 100 has recesses 170, 180 resulting from the different levels of the upper surfaces of pad nitride layer 130 and strap layers 149, 159. The recesses 170, 180 include step portions 171, 172, 181, and 182 formed at the respective edges between the upper surface of the pad nitride layer 130 and the upper surfaces of the strap layers 149, 159 of the first and second deep trench configurations 142, 152. The step portions 171, 172, 181 and 182 may have a height of, for example, about 2000 Angstroms. In order to have a desired pattern or shallow trench etching mask, resist should be developed as shown in FIG. 2, with a definitive edge at the middle of the strap layer, which is recessed from the surface level of the semiconductor substrate 110. However, when resist is applied to a surface that has step formations, light passes through the resist and reflects from both the substrate surface and the recessed surface. The light reflected from the recessed surface interferes with incoming light differently than the light reflected from the substrate surface thereby causing an undesirable resist profile after development. The interference pattern and, as a consequence, the resist profile are dependent on the height of the step. Thus, resolution at the edge of the resist profile is poor and very sensitive to variations in step height. Accordingly, the process window for lithography is narrow and repeatability of the process is impaired.
Furthermore, etching the shallow trench is itself difficult because the semiconductor substrate region 115, portions of the intrinsic polysilicon strap layers 149, 159, portions of the thin nitride insulator 144, 154, portions of thick oxide insulator 146, 156, portions of n+ polysilicon storage node material 147, 157, the pad nitride region 135, and the pad oxide region 125 must all be removed. While the pad nitride region 135 and the pad oxide region 125 may be etched using a process selective to silicon, a simultaneous, multi-material etch of polysilicon, nitride, and oxide is required. The problem is compounded by the fact that the polysilicon, nitride, and oxide do not form a planar surface. Therefore, an extremely non-selective etching technique is required.
Moreover, as noted above, lithography produces poor resolution of the edges of resist above the deep trench configurations 142, 152. Because etching processes for forming tapered trenches are more susceptible to inaccuracies caused by resist profile variation, shallow trenches are formed by etching processes that produce highly vertical trench profiles. In addition, tapered shallow trenches are more vulnerable to misalignment. To minimize the adverse effect of poor resolution of lithography and misalignment, vertical etching is required.
The requirement of a vertical trench profile conflicts with the requirement of non-selective etching. This imposes severe restrictions on the etching procedure. For example, a deposition-type etching process that forms a deposition film on the vertical plane cannot be used because the film also deposits on the horizontal plane of each material differently and thus induces etching rate disparities between materials. Accordingly, the resulting etch becomes selective which is inconsistent with the requirement of non-selectivity. However, it is difficult to control the trench profile without an etching process that also forms a deposition film. Due to the rigid restrictions placed upon the etching procedure, even a slight variation in etching conditions produces a relatively large decrease in etching performance.
Further, there is at least one problem inherent in transistors delineated and isolated by shallow trenches having a highly vertical profile. Sharp corners formed by the shallow trench sidewall and the semiconductor substrate surface modify the local electric field distribution so as to reduce the local threshold voltage. Accordingly, the threshold voltage of the channel region adjacent to the shallow trench sidewall has a lower value than that at the center of the channel region. The lower threshold at the corner is detrimental to the cut-off characteristics of the transistor and may cause leakage current. For peripheral circuitry, which contains relatively large transistors having relatively large currents, the leakage current produces significant power dissipation. The leakage current in switching transistors, which are connected to the storage nodes, leads to the discharge of the storage nodes and thus a loss of information.
In order to obtain a good quality interface between the silicon and the shallow trench sidewall, thermal oxidation of the shallow trench interior surface is preferable. However, during this oxidation step, oxidant diffuses through the exposed thick oxide insulator and induces undesired oxidation of silicon in its vicinity. In addition, the interior surface of the storage node voids 148, 158, which may be formed of n+ polysilicon, as noted above, may be oxidized. Oxidation of silicon causes a volume expansion. Stress resulting from the expansion can lead to crystal defects such as dislocations in the crystal silicon semiconductor substrate. Such crystal defects modify the electrical properties of the semiconductor and cause junction leakage currents. Consequently, the retention time of a memory cell device, as well as other important characteristics, may be impaired. Accordingly, there exists a need to provide a method for forming a shallow trench between deep trench configurations that is easily implemented and that avoids the difficulties and disadvantages of conventional methods.